A Gate-Controlled Supercurrent-Based Non-Volatile Memory Device
Abstract
Promising gate-controlled superconducting non-volatile memory elements deliver cryogenic operation, high storage density, and ultra-low power consumption by modulating critical current via gate voltage in nanoscale constrictions.
Advantages
- High Density & Scalability: Nanoscale fabrication compatible with standard CMOS processes
- Ultra-Low Energy: < 10 aJ/bit at 4 K, no refresh cycles
- High Speed: > 10 GHz switching, recovery < 5 ns
- Cryogenic Non-Volatility: Retains state at 0.001–80 K and in magnetic fields up to 10 T
- Multi-Level Cell Capability: Up to 2 bits per cell, enabling 3D-NAND arrays
Fields of application
- Superconducting high-performance and quantum computing
- Cryo-CMOS hybrid circuits and single-flux-quantum logic
- Energy-efficient data storage in helium-cooled sensor networks
- Space and particle-physics detectors under high magnetic fields
Background
Conventional computing architectures employ CMOS for volatile logic and Flash for non-volatile storage. Emerging superconducting processors promise orders-of-magnitude lower energy dissipation but lack compatible non-volatile memory architectures operable at cryogenic temperatures.
Problem
No existing superconducting non-volatile memory element combines CMOS-scale integration, low fabrication cost, and high density with the switching speed and near-zero static losses of superconductors.
Solution
The invention comprises a gate-controlled superconducting memory cell featuring:
- A NbN nano-constriction (10 nm width) whose critical current Ic is permanently modulated by gate voltage
- A conformal 3 nm Al₂O₃ charge-trap dielectric providing two stable states (charged/uncharged)
- A wrap-around TiN gate electrode enabling precise Ic(VG) tuning
Multi-stacked constrictions enable 3D-NAND-style architectures.
![[Translate to english:] Photorealistische Schnittdarstellung einer gate-gesteuerten, supraleitenden nichtflüchtigen Speicherzelle für den Betrieb bei kryogenen Temperaturen (~4 K). Der zentrale NbN-Nanodraht (10 nm) verbindet zwei supraleitende Source-/Drain-Kontakte auf einem Saphir-Substrat. Umhüllt wird die Constriction von einem 3 nm dünnen Al₂O₃-Charge-Trap-Dielektrikum und einer umlaufenden TiN-Gateelektrode. Zwei Speicherzustände werden visualisiert: (A) „Aus“ mit reduziertem kritischem Strom, (B) „Ein“ mit erhöhter Cooperpaar-Dichte – erkennbar am leuchtenden blauen Schimmer. Diagramm-Inset zeigt die Abhängigkeit von Ic(VG) bei geladener bzw. ungeladener Dielektrikumsfalle. (HJ Eisler)](/fileadmin/user_upload/img/Technologieangebote/24_053_Abb_1.png "Figure 1. Photorealistic sectional view of a gate-controlled superconducting non-volatile memory cell operating at cryogenic temperatures.
This cross-sectional illustration presents the architectural design of a superconducting memory device optimized for operation at approximately 4 K. The device structure comprises a 10-nanometer-wide niobium nitride (NbN) nanowire that establishes electrical connectivity between two superconducting source and drain contacts deposited on a sapphire substrate. The nanowire constriction region is encapsulated within a 3-nanometer-thick aluminum oxide (Al₂O₃) dielectric layer that functions as a charge trapping medium. A titanium nitride (TiN) gate electrode surrounds the dielectric-encased constriction to enable electrostatic control of the device.
The visualization demonstrates the two primary memory states through distinct representations. Panel A depicts the \"off\" state, characterized by suppressed critical current flow through the nanowire constriction. Panel B illustrates the \"on\" state, wherein the bright blue artistic rendering represents the enhanced Cooper pair density within the superconducting channel. This visual effect serves as an artistic representation to illustrate the increased superconducting carrier concentration rather than an actual optical phenomenon. The inset diagram quantifies the relationship between critical current and gate voltage [Ic(VG)], demonstrating the modulation effect induced by charge accumulation or depletion within the Al₂O₃ trap sites.
This device architecture represents a fundamental building block for cryogenic quantum memory systems, providing non-volatile storage functionality through gate-controlled manipulation of superconducting transport properties. (HJ Eisler)")
Figure 1. Photorealistic sectional view of a gate-controlled superconducting non-volatile memory cell operating at cryogenic temperatures.
This cross-sectional illustration presents the architectural design of a superconducting memory device optimized for operation at approximately 4 K. The device structure comprises a 10-nanometer-wide niobium nitride (NbN) nanowire that establishes electrical connectivity between two superconducting source and drain contacts deposited on a sapphire substrate. The nanowire constriction region is encapsulated within a 3-nanometer-thick aluminum oxide (Al₂O₃) dielectric layer that functions as a charge trapping medium. A titanium nitride (TiN) gate electrode surrounds the dielectric-encased constriction to enable electrostatic control of the device.
The visualization demonstrates the two primary memory states through distinct representations. Panel A depicts the "off" state, characterized by suppressed critical current flow through the nanowire constriction. Panel B illustrates the "on" state, wherein the bright blue artistic rendering represents the enhanced Cooper pair density within the superconducting channel. This visual effect serves as an artistic representation to illustrate the increased superconducting carrier concentration rather than an actual optical phenomenon. The inset diagram quantifies the relationship between critical current and gate voltage [Ic(VG)], demonstrating the modulation effect induced by charge accumulation or depletion within the Al₂O₃ trap sites.
This device architecture represents a fundamental building block for cryogenic quantum memory systems, providing non-volatile storage functionality through gate-controlled manipulation of superconducting transport properties. (HJ Eisler)
Publications and links
- R. Ruf et al., A Gate-Controlled Supercurrent-Based Non-Volatile Memory Device, PCT/EP2025/056297.
- US 10 236 433 B1; US 11 165 429 B2; WO 2025/034194 A2 (Stand der Technik)